3rd Digital IndiaRISC-V (DIR-V)Symposium

Empowering Bharat's semiconductor future through secure, indigenous RISC-V systems.

Message from Director

The third edition builds on two successful gatherings of students, startups, government organisations, researchers, and industry practitioners.

Kamakoti Veezhinathan
Kamakoti Veezhinathan Director, IIT Madras

“The Digital India RISC-V symposium began as an initiative to bring together strategic partners across government, industry, and academia. The idea was to engage with our fellow RISC-V practitioners in the RISC-V ecosystem to understand the challenges and opportunities for advancing the indigenous semiconductor movement.

From the very first edition, our intent was to sit with our fellow practitioners in the RISC-V ecosystem, listen carefully to the challenges on the ground, and collectively chart a course for advancing an indigenous semiconductor movement that is both credible and self-sustaining.

The first two editions gave us more than we anticipated. Seeing students, startups, and government organisations engage reaffirmed what many of us at IIT Madras have long believed. that India possesses the intellectual capital and institutional will to lead, not merely participate, in the global semiconductor story.

It is from that foundation of confidence, and with a sharpened sense of purpose, that we launch the third edition of the DIR-V Symposium. As India's Digital Transformation initiatives reach unprecedented scale, one reality becomes inescapable: none of it holds without security. Security is not a feature to be added later. It is the architecture itself. And when the silicon beneath our digital systems is designed and verified here, on Indian soil, with Indian hands, the question of who controls that security layer becomes not merely technical, but strategic.

This is why the theme of the third edition of the DIR-V Symposium is Security. We invite you, our partners, startups, students, and fellow researchers to join us in this symposium and share your thoughts, ideas on how RISC-V ecosystem can be a key component in imagining a safe and secure Digital Future for our country.

I invite you all to join us in what I believe will be our most consequential gathering yet.

Thank you,
Prof. V. Kamakoti
Director, IIT Madras”

What to expect

A focused two-day forum for ideas, demos, funding conversations, and hands-on work around secure RISC-V adoption.

01

Tech Talks & Keynotes

Engage with thought leaders who are shaping the global RISCV ecosystem and contributing to the work at RKCoE, advancing the field of opensource ISAs and processor design.

02

Investor Meetings

Showcase your RISC-V innovations and explore potential funding and collaboration opportunities to bring your ideas to life.

03

Hands-on Workshops & Hackathons

Dive into workshops and hackathons centered around RISC-V product development, FPGA prototyping, core enhancements, and systems software, exploring real-world applications.

04

Networking Opportunities

Connect with key members of the ACT community, innovators, and investors who are contributing to the future of RISC-V-based solutions and India’s growing role in the semiconductor industry.

Our Sponsors

Partner with India's secure RISC-V ecosystem and put your brand in front of researchers, startups, students, investors, and semiconductor leaders.

DIR-V momentum

From roadshows to tapeouts, the ecosystem is turning national ambition into practical semiconductor capability.

2Workshops
3Roadshows
2Tapeouts
2500+Students reached

Speakers

Keynotes, panels, and technical sessions will feature leaders from the secure RISC-V ecosystem.

Speaker lineup will be announced soon

We are curating voices from academia, government, startups, and industry to bring sharp perspectives on security, AI, silicon, and India's RISC-V future.

Coming Soon Confirmed names to follow

Tentative agenda

Security, AI, grand challenge outcomes, exhibitions, technical sessions, and community exchange. Timings and sessions may be updated.

Day 1

Saturday, 1 August 2026
TimeSession
Registration
Inaugural Ceremony
Welcome Address
Guest of Honours Address
Hackathon Results
Tea Break
Keynote Address - 1
Panel Discussion - 1: Security in the Age of RISC-V
Lunch + Visit to Exhibition Stalls
Keynote Address - 2
Grand Challenge Hackathon Presentation
Briefing for Day - 2

Day 2

Sunday, 2 August 2026
TimeSession
Follow-up for Day 1 & Context for Day 2
Keynote Address - 3
Technical Session - 1
Tea Break
Panel Discussion - 2: RISC-V in the Age of AI
Technical Session - 2
Lunch + Exhibition Stalls
Technical Session - 3
Technical Session - 4
Special Address
Closing Remarks

Sponsorship packages

Support the forum and gain visibility with India's secure RISC-V ecosystem. Package details are captured from the sponsorship sheet.

Benefit
Silicon
Platinum
Gold
Startup
Investment
in Lakhs (₹)
10
5
3
1
Available Slots
2
5
8
15
Passes
10
5
3
1
Branding & visibility
Logo in main stage & banner
Yes
Yes
Yes
-
Logo in all print & digital collateral
Yes
Yes
Yes
Yes
Logo on event website
Yes
Yes
Yes
Yes
Social media mentions
Dedicated post
Dedicated post
Grouped post
-
Speaking & presence
Keynote Slot
Yes
-
-
-
Panel participation
Yes
Yes
-
-
Exhibition / Demo Stall
6x6 m
4x4 m
3x4 m
2x2 m
Programmes
Hackathons
Yes
Yes
-
-
Workshops
Yes
Yes
Yes
-

Swipe the table horizontally to compare all package columns.

Organising Committee

Committee members guiding the planning and execution of the DIR-V Symposium.

Steering Committee

V. Kamakoti
V. Kamakoti Director, IIT Madras
Chester Rebeiro
Chester Rebeiro Professor, CSE Department, IIT Madras
Gopalakrishnan S
Gopalakrishnan S Assistant Professor, CSE Department, IIT Madras
Patanjali SLPSK
Patanjali SLPSK Assistant Professor, DSAI Department, IIT Madras

Executive Committee

Mathanan Kailas
Mathanan Kailas Director Strategy & Operations, CyStar, IIT Madras
Lavanya J
Lavanya J CEO/Founder, Vyoma Systems; Principal Project Officer, Shakti Group, IIT Madras

Organising ecosystem

Convened by IIT Madras with national and international RISC-V ecosystem partners.

IIT Madras IITM Pravartak MeitY India Semiconductor Mission RISC-V SHAKTI

Contact

Reach the relevant team for sponsorship, hospitality, registration, student challenge, or general symposium queries.

Category Purpose Contact Person Email
Sponsorship Corporate packages and partnership opportunities. Lavanya Jagan lavanya@vyomasystems.com
Hospitality Accommodation and hospitality-related queries. Jessy sec-vkama@cse.iitm.ac.in
Grand Student Challenge Student team submissions and guidelines. Kotteeswaran kottee.off@gmail.com
Registration Event registration and assistance. Haribaskar M haribaskar@cystar.iitm.ac.in
General Inquiries Overall event-related queries and feedback. Jessy sec-vkama@cse.iitm.ac.in
Haribaskar M haribaskar@cystar.iitm.ac.in